During product development of integrated circuits, prototype circuits can be physically edited to debug an integrated circuit design. Circuit editing involves an alteration of interconnect routing by, e.g., drilling vias through a backside of a chip to interconnections in the chip and depositing metal in the vias to alter the connections between device active areas. Devices on a chip can thereby be connected in alternative ways, facilitating post-processing troubleshooting.
Prior to the formation of this type of via, the backside of a silicon chip is thinned by, e.g., focused ion beam etching, also known as ion milling. Typically, a timed etch is performed based on the expected etch rate and the expected silicon thickness. A timed etch can be problematic, especially in the case of variable etch rates and silicon thicknesses. The thickness of silicon remaining after a timed etch typically falls within a wide range such as 4-5 microns (μm)±2 μm, leading to unreliability in subsequent processing, such as via formation. Further, thinning the chip too much can damage the device which one wishes to contact. For example, etching into a diffused region can adversely affect device performance.
An alternative to timed etching includes photo current endpoint/real time optical beam induced current (PCEP/RT-OBIC) technique. This technique has the drawback of requiring the installation of additional hardware. A further limitation of the PCEP/RT-OBIC technique is that it does not provide an endpoint curve if the area being milled has >30% decoupling capacitors, i.e. capacitors for noise filtering, or if the mill box size, i.e. the area scanned by an ion beam during etching, is less than 100 μm×100 μm.